The Design and Evaluation of a Selective Way Based Trace Cache

Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, but the energy for accessing the other ways is wasted. In this paper, we propose a selective way based trace cache (SWTC), which probes only the selected way(s) instead of probing all the data ways. In SWTC, traces are divided into several types and stored into cache by type. Then the trace cache is partially activated and accessed. Based on these design principles, a SWTC model is proposed and evaluated in this paper. Simulation results show that compared to CTC, SWTC can reduce energy consumption on the fetch unit by 20.1% on average, while providing almost the same performance in terms of number of instructions per cycle.